The present disclosure relates to fabricating semiconductor devices. More particularly, the present disclosure relates to forming gate structures and making contacts to source and drain regions of a semiconductor structure.
Transistors, such as field effect transistors (FETs) are the basic elements of microelectronics and integrated circuits. There has been a continuous drive to scale down or shrink transistors and other semiconductor devices to increase density and improve processing performance. One technique that is used to fabricate transistors is known as a replacement metal gate (RMG) process. A replacement metal gate process involves creating a sacrificial or dummy gate during fabrication, and then later replacing the dummy gate with a metal gate electrode. Such a replacement technique can be used to fabricate metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS), which can be types of fin field effect transistors (FinFETs).
In a replacement metal gate fabrication process, a transistor can be fabricated using a dummy gate electrode. The dummy gate electrode can be made from a polysilicon material. This can be beneficial because polysilicon is able to tolerate high temperature processing better than most metals. Thus, polysilicon can be annealed at higher temperatures along with source and drain regions. In one RMG process flow, a dummy gate electrode is formed and then a source region and a drain region are formed adjacent to the dummy gate. The dummy gate is eventually replaced by a gate stack that can including a high dielectric constant (high-k) gate dielectric and/or a metal gate. Forming the gate stack after high temperature processing steps can result in minimal damage on the high-k gate dielectric and the metal gate. Additionally, a wider range of metals can be selected for the gate conductor.
After a dummy gate is replaced with a final gate or gate state, contacts can be made to the source and drain. Creating such contacts typically involves etching through one or more layers on a substrate. This etching can be assisted with etch masks patterned using lithography techniques. With etched openings created to source and drain regions, metal contacts can be formed and semiconductor fabrication continued to subsequent steps, such as interconnect or wiring steps.